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CCM4208S is a multi-function microcontroller (MCU) based on the Cortex-M4Fcore. It is distinguished by low power consumption, high performance, multifunction and high security level. With built-in hardware acceleration engines for QR codes and face recognition, it is widely applicable in scenarios like QR code scanning, fingerprint recognition, face recognition, smart homes, and security video monitoring. The chip’s typical operating frequency is 400MHz.
Block diagram of CCM4208S
Package Type
| Pin | Package type and pin assignment(mm) | |
LQFP128(14*14*1.6) | BGA169(9*9*1.27) | |
SPI | 3 | 3 |
I2C | 3 | 2 |
SSI | 2 | 1 |
SCI | 4 | 4 |
ISO7816 | 1 | 1 |
USB_OTG | 1 | 2 |
ADC | 6 | 6 |
DAC | 1 | 1 |
PWM(Multiplexing) | 8 | 8 |
MCC | 1 | 1 |
TSI(Multiplexing) | 0 | 16 |
SDIO | 8 | 8 |
I2S（Multiplexing） | 1 | 1 |
CAN（Multiplexing） | 1 | 1 |
SD Host | 1 | 1 |
MIPI | 1 | 1 |
DCMI | 1 | 1 |
LCD | 1 | 1 |
WAKE UP | 1 | 1 |
MAC(Multiplexing) | 1 | 1 |
• 32-bit high-performance Cortex-M4F
• Operating frequency:500MHz
• Supporting DSP instructions
• Supporting single-precision floating-point unit (FPU)
• Memory protection unit (MPU)
• 64KB Cache
• External bus supporting 8bit/16bit/32bit access
• Support for hardware-secured access control of peripheral components
• Nested vectored interrupt controller (NVIC) for low-latency, low-jitter interrupt response
• Low power consumption with high performance
• 128KB SRAM + 64KB TCM SRAM
• 64KB ROM
• 256KB EFLASH with 512 bytes/Page and a minimum of 100,000 erase cycles Expandable up to 64MB SDRAM and 16MB SPIFLASH
• DMA/EDMA
• 4 timers (PIT32)
• Watchdog timer (WDT)
• Time counter (TC)
• Real-time clock (RTC)
● Asymmetric algorithms
- 2048bit RSA
- 256bit SM2 prime field
- 256bit ECC prime field
● Symmetric algorithms
- DES/3DES supports ECB/CBC mode
- AES supports ECB/CBC/CFB/OFB and CTR modes
- SM4 supports ECB/CBC/CFB/OFB modes
● Hashing algorithms
- SM3
- SHA-0/ SHA-1/ SHA-224/ SHA-256/ SHA-384/ SHA-512
• Supporting CRC32/ CRC16/ CRC8
• Supporting DMAC operations
• Supporting EDMAC operations
● Memory protection mechanism
- Application-oriented memory partitioning with hardware support for secure isolation
- Scrambling bus
● True random number generator, compliant with FIPS 140-2 standards and national commercial cryptography standards
• Voltage detection unit
• Light detection unit
• Power supply burr detection unit
• Metal shielding protection
• Temperature detection unit
• Frequency detection unit
• Clock and reset pulse filtering
• Optimizing wire routing for security
• Supporting 128 Byte NVSRAM
• Supporting 4 pairs of open cover detection signals, configured with dynamic/static detection mode
• Supporting voltage detection
• Supporting temperature detection
• Supporting self-destruct and clear NVSRAM
● Each product has a unique serial number
● Main power input voltage: 2.97V~5.5V, PCI domain input voltage: 2V~3.3V
● Core clock frequency: 400MHz
● typical power consumption: 80mA
● Three low-power modes
- 1024bit RSA
- 2048bit RSA
- 256bit SM2 prime field
● Supporting for internal power-on reset and external reset
• Level II of security chip for commercial Crypto product certification
• Terminal Chip Security Assessment (compliant with PCI 6.0)
• Face recognition
• Financial payment
• Label printers
• Complete development environment
• Rich driver libraries
• Complete application solutions
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